The present invention relates generally to the field of level shifters, and more particularly to a cascode complementary dual level shifter.
CMOS technologies include thin- and thick-oxide field-effect transistors (“FET(s)”) to deal with regular drain supply voltage (“VDD”), for example, 0.8V, and high peak to peak voltage (“VPP”), for example, 1.6V. At around a 14 nm technology node, the FET type was changed to fin from planar to scale further, which may result in thin-oxide FET only circuits to reduce significantly increased manufacturing and development costs. Cascode methods enable thin-oxide FET only circuits to shift between regular and high voltage. A cross-coupled inverter gate (“INV”) may be vulnerable to metastability, associated with poor cascade p-channel FET (“PFET”) pull-up current capability, where there is a low absolute gate-to-source voltage (“Vgs”). This Vgs may cause the pFET to malfunction or get stacked an undesired state. It may be advantageous to mitigate issues in poor performing FETs or FETs stacked in an undesired state.